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lt3023 1 3023fa typical application features applications description dual 100ma, low dropout, low noise, micropower regulator the lt ? 3023 is a dual, micropower, low noise, low drop- out regulator. with an external 0.01f bypass capacitor, output noise drops to 20v rms over a 10hz to 100khz bandwidth. designed for use in battery-powered systems, the low 20a quiescent current per channel makes it an ideal choice. in shutdown, quiescent current drops to less than 0.1a. shutdown control is independent for each channel, allowing for ? exibility in power management. the device is capable of operating over an input voltage from 1.8v to 20v, and can supply 100ma of output current from each channel with a dropout voltage of 300mv. quiescent current is well controlled in dropout. the lt3023 regulator is stable with output capacitors as low as 1f. small ceramic capacitors can be used without the series resistance required by other regulators. internal protection circuitry includes reverse battery protection, current limiting, thermal limiting and reverse current protection. the device is available as an adjust- able device with a 1.22v reference voltage. the lt3023 regulator is available in the thermally enhanced 10-lead msop and dfn packages. n low noise: 20v rms (10hz to 100khz) n low quiescent current: 20a/channel n wide input voltage range: 1.8v to 20v n output current: 100ma/channel n very low shutdown current: <0.1a n low dropout voltage: 300mv at 100ma n adjustable output from 1.22v to 20v n stable with 1f output capacitor n stable with aluminum, tantalum or ceramic capacitors n reverse battery protected n no reverse current n no protection diodes needed n overcurrent and overtemperature protected n thermally enhanced 10-lead msop and dfn packages n cellular phones n pagers n battery-powered systems n frequency synthesizers n wireless modems l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 10hz to 100khz output noise 3.3v/2.5v low noise regulators in shdn2 0.01f 0.01f 10f 3023 ta01 out1 v in 3.7v to 20v byp1 adj1 out2 byp2 adj2 gnd lt3023 3.3v at100ma 20v rms noise 2.5v at100ma 20v rms noise 1f shdn1 10f 422k 249k 261k 249k v out 100v/div 20v rms 3023 ta01b
lt3023 2 3023fa absolute maximum ratings in pin voltage .........................................................20v out1, out2 pin voltage .........................................20v input to output differential voltage .........................20v adj1, adj2 pin voltage ............................................7v byp1, byp2 pin voltage ........................................0.6v shdn1, shdn2 pin voltage ...................................20v (note 1) top view dd package 10-lead ( 3mm s 3mm ) plastic dfn 10 9 6 7 8 4 5 3 2 1 out2 shdn2 in shdn1 out1 byp2 adj2 gnd adj1 byp1 11 t jmax = 125c, = = ( ) = = = ( ) ( ) ( ) ( ) ( ) . . .. .. ........................... ( ) ............................................. ................... ( ) .................. ( ) = . ( ) ( ) = . . ( ) = = . . . . . . .
lt3023 3 3023fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3023 is tested and speci? ed under pulse load conditions such that t j t a . the lt3023e is 100% tested at t a = 25c. performance at C 40c and 125c is assured by design, characterization and correlation with statistical process controls. the lt3023i is guaranteed over the full C40c to 125c operating junction temperature range. note 3: the lt3023 is tested and speci? ed for these conditions with the adj1/adj2 pin connected to the corresponding out1/out2 pin. note 4: operating conditions are limited by maximum junction temperature. the regulated output voltage speci? cation will not apply for all possible combinations of input voltage and output current. when operating at maximum input voltage, the output current range must be limited. when operating at maximum output current, the input voltage range must be limited. note 5: to satisfy requirements for minimum input voltage, the lt3023 is tested and speci? ed for these conditions with an external resistor divider (two 250k resistors) for an output voltage of 2.44v. the external resistor divider will add a 5a dc load on the output. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 2) parameter conditions min typ max units line regulation (note 3) v in = 2v to 20v, i load = 1ma l 110 mv load regulation (note 3) v in = 2.3v, i load = 1ma to 100ma v in = 2.3v, i load = 1ma to 100ma l 112 25 mv mv dropout voltage v in = v out(nominal) (notes 5, 6, 11) i load = 1ma i load = 1ma l 0.10 0.15 0.19 v v i load = 10ma i load = 10ma l 0.17 0.22 0.29 v v i load = 50ma i load = 50ma l 0.24 0.28 0.38 v v i load = 100ma i load = 100ma l 0.30 0.35 0.45 v v gnd pin current (per channel) v in = v out(nominal) (notes 5, 7) i load = 0ma i load = 1ma i load = 10ma i load = 50ma i load = 100ma l l l l l 20 55 230 1 2.2 45 100 400 2 4 a a a ma ma output voltage noise c out = 10f, c byp = 0.01f, i load = 100ma, bw = 10hz to 100khz 20 v rms adj1/adj2 pin bias current (notes 3, 8) 30 100 na shutdown threshold v out = off to on v out = on to off l l 0.25 0.8 0.65 1.4 v v shdn1 / shdn2 pin current (note 9) v shdn = 0v v shdn = 20v l l 0 1 0.5 3 a a quiescent current in shutdown v in = 6v, v shdn = 0v (both shdn pins) 0.01 0.1 a ripple rejection (note 3) v in = 2.72v (avg), v ripple = 0.5v p-p , f ripple = 120hz, i load = 50ma 55 65 db current limit v in = 7v, v out = 0v v in = 2.3v, v out = C5% l 110 200 ma ma input reverse leakage current v in = C20v, v out = 0v l 1ma reverse output current (notes 3,10) v out = 1.22v, v in < 1.22v 5 10 a note 6: dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a speci? ed output current. in dropout, the output voltage will be equal to: v in C v dropout . note 7: gnd pin current is tested with v in = 2.44v and a current source load. this means the device is tested while operating in its dropout region or at the minimum input voltage speci? cation. this is the worst-case gnd pin current. the gnd pin current will decrease slightly at higher input voltages. note 8: adj1 and adj2 pin bias current ? ows into the pin. note 9: shdn1 and shdn2 pin current ? ows into the pin. note 10: reverse output current is tested with the in pin grounded and the out pin forced to the rated output voltage. this current ? ows into the out pin and out the gnd pin. note 11: for the lt3023 dropout voltage will be limited by the minimum input voltage speci? cation under some output voltage/load conditions. see the curve of minimum input voltage in the typical performance characteristics.
lt3023 4 3023fa output current (ma) 500 450 400 350 300 250 200 150 100 50 0 dropout voltage (mv) 3023 g01 0 102030 40 50 60 70 80 90 100 t j = 125c t j = 25c output current (ma) 500 450 400 350 300 250 200 150 100 50 0 dropout voltage (mv) 3023 g02 0 102030 40 50 60 70 80 90 100 t j 125c t j 25c = test points temperature (c) C50 dropout voltage (mv) 0 50 75 3023 g03 C25 25 100 125 i l = 100ma i l = 50ma i l = 10ma i l = 1ma 500 450 400 350 300 250 200 150 100 50 0 typical performance characteristics typical dropout voltage guaranteed dropout voltage dropout voltage quiescent current adj1 or adj2 pin voltage quiescent current gnd pin current gnd pin current vs i load shdn1 or shdn2 pin threshold (on-to-off) temperature (c) C50 quiescent current (a) 100 3023 g03 050 40 35 30 25 20 15 10 5 0 C25 25 75 125 v in = 6v r l = 250k i l = 5a v shdn = v in v shdn = 0v temperature (c) C50 adj pin voltage (v) 100 3023 g05 050 1.240 1.235 1.230 1.225 1.220 1.215 1.210 1.205 1.200 C25 25 75 125 i l = 1ma input voltage (v) 02 6 10 14 18 quiescent current (a) 30 25 20 15 10 5 0 4 8 12 16 3023 g06 20 t j = 25c r l = 250k i l = 5a v shdn = v in v shdn = 0v input voltage (v) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 gnd pin current (ma) 3023 g07 0123 4 5 67 8910 t j = 25c *for v out = 1.22v r l = 12.2 i l = 100ma* r l = 24.4 i l = 50ma* r l = 122 i l = 10ma* r l = 1.22k i l = 1ma* output current (ma) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 gnd pin current (ma) 3023 g08 0 102030 40 50 60 70 80 90 100 v in = v out(nominal) + 1v temperature (c) C50 shdn pin threshold (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 50 75 3023 g09 C25 25 100 125 i l = 1ma
lt3023 5 3023fa typical performance characteristics shdn1 or shdn2 pin threshold (off-to-on) shdn1 or shdn2 pin input current shdn1 or shdn2 pin input current adj1 or adj2 pin bias current current limit current limit reverse output current reverse output current input ripple rejection temperature (c) C50 shdn pin threshold (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 50 75 3023 g10 C25 25 100 125 i l = 100ma i l = 1ma shdn pin voltage (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 shdn pin input current (a) 3023 g11 0123 4 5 67 8910 temperature (c) C50 shdn pin input current (a) 0 50 75 3023 g12 C25 25 100 125 v shdn = 20v 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 temperature (c) C50 adj pin bias current (na) 100 90 80 70 60 50 40 30 20 10 0 0 50 75 3023 g13 C25 25 100 125 input voltage (v) 0 short-circuit current (ma) 2 4 5 3023 g14 1 3 6 7 350 300 250 200 150 100 50 0 v out = 0v t j = 25c temperature (c) C50 current limit (ma) 0 50 75 3023 g15 C25 25 100 125 350 300 250 200 150 100 50 0 v in = 7v v out = 0v output voltage (v) 100 90 80 70 60 50 40 30 20 10 0 reverse output current (a) 3023 g16 0123 4 5 67 8910 t a = 25c v in = 0v v out = v adj current flows into output pin temperature (c) C50 reverse output current (a) 18 15 12 9 6 3 0 25 75 3023 g17 C25 0 50 100 125 v in = 0v v out = v adj = 1.22v frequency (khz) ripple rejection (db) 80 70 60 50 40 30 20 10 0 0.01 1 10 1000 3023 g18 0.1 100 i l = 100ma v in = 2.3v + 50mv rms ripple c byp = 0 c out = 10f c out = 1f
lt3023 6 3023fa typical performance characteristics input ripple rejection input ripple rejection channel-to-channel isolation channel-to-channel isolation minimum input voltage load regulation output noise spectral density output noise spectral density rms output noise vs bypass capacitor frequency (khz) ripple rejection (db) 80 70 60 50 40 30 20 10 0 0.01 1 10 1000 3023 g19 0.1 100 i l = 100ma v in = 2.3v + 50mv rms ripple c out = 10f c byp = 0.01f c byp = 1000pf c byp = 100pf temperature (c) C50 ripple rejection (db) 100 3023 g20 050 80 70 60 50 40 30 20 10 0 C25 25 75 125 v in = v out (nominal) + 1v + 0.5v p-p ripple at f = 120hz i l = 50ma 50s/div c out1 , c out2 = 10f c byp1 , c byp2 = 0.01f i l1 = 10ma to 100ma i l2 = 10ma to 100ma v in = 6v, v out1 = v out2 = 5v v out1 20mv/div v out2 20mv/div 3023 g21a frequency (khz) channel-to-channel isolation (db) 100 90 80 70 60 50 40 30 20 10 0 0.01 1 10 1000 3023 g21b 0.1 100 i load = 100ma per channel temperature (c) C50 minimum input voltage (v) 2.5 2.0 1.5 1.0 0.5 0 0 50 75 3023 g22 C25 25 100 125 i l = 100ma i l = 50ma temperature (c) C50 load regulation (mv) 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 05075 3023 g23 C25 25 100 125 il = 1ma to 100ma frequency (khz) output noise spectral density (v/ hz ) 0.01 1 10 100 3023 g24 0.1 10 1 0.1 0.01 v out set for 5v v out =v adj c out = 10f c byp = 0 i l = 100ma frequency (khz) output noise spectral density (v/ hz ) 0.01 1 10 100 3023 g25 0.1 10 1 0.1 0.01 v out set for 5v v out =v adj c out = 10f i l = 100ma c byp = 1000pf c byp = 100pf c byp = 0.01f c byp (pf) 10 output noise (v rms ) 160 140 120 100 80 60 40 20 0 100 1k 10k 3023 g26 v out set for 5v v out =v adj c out = 10f i l = 100ma f = 10hz to 100khz
lt3023 7 3023fa typical performance characteristics rms output noise vs load current (10hz to 100khz) 10hz to 100khz output noise c byp = 0 10hz to 100khz output noise c byp = 100pf 10hz to 100khz output noise c byp = 1000pf 10hz to 100khz output noise c byp = 0.01f transient response c byp = 0 transient response c byp = 0.01f load current (ma) 0.01 output noise (v rms ) 160 140 120 100 80 60 40 20 0 0.1 1 100 10 3023 g27 v out set for 5v v out set for 5v v out =v adj v out =v adj c out = 10f c byp = 0f c byp = 0.01f time (s) 0.2 0.1 0 C0.1 C0.2 output voltage deviation (v) 100 50 0 load current (ma) 3023 g32 0 400 800 1200 1600 2000 v in = 6v c in = 10f c out = 10f v out set for 5v out time (s) 0.04 0.02 0 C0.02 C0.04 output voltage deviation (v) 100 50 0 load current (ma) 3023 g33 0 40 60 100 20 80 120 140 180 160 200 v in = 6v c in = 10f c out = 10f v out set for 5v out 1ms/div c out = 10f i l = 100ma v out set for 5v out v out 100v/div 3023 g28 1ms/div c out = 10f i l = 100ma v out set for 5v out v out 100v/div 3023 g29 1ms/div c out = 10f i l = 100ma v out set for 5v out v out 100v/div 3023 g30 1ms/div c out = 10f i l = 100ma v out set for 5v out v out 100v/div 3023 g31
lt3023 8 3023fa pin functions gnd (pin 3): ground. adj1/adj2 (pins 4/2): adjust pin. these are the inputs to the error ampli? ers. these pins are internally clamped to 7v. they have a bias current of 30na which ? ows into the pin (see curve of adj1/adj2 pin bias current vs tempera- ture in the typical performance characteristics section). the adj1 and adj2 pin voltage is 1.22v referenced to ground and the output voltage range is 1.22v to 20v. byp1/byp2 (pins 5/1): bypass. the byp1/byp2 pins are used to bypass the reference of the lt3023 regulator to achieve low noise performance from the regulator. the byp1/byp2 pins are clamped internally to 0.6v (one v be ) from ground. a small capacitor from the corresponding output to this pin will bypass the reference to lower the output voltage noise. a maximum value of 0.01f can be used for reducing output voltage noise to a typical 20v rms over a 10hz to 100khz bandwidth. if not used, this pin must be left unconnected. out1/out2 (pins 6/10): output. the outputs supply power to the loads. a minimum output capacitor of 1f is required to prevent oscillations. larger output capacitors will be required for applications with large transient loads to limit peak voltage transients. see the applications information section for more information on output capacitance and reverse output characteristics. shdn1 / shdn2 (pins 7/9): shutdown. the shdn1 / shdn2 pins are used to put the corresponding channel of the lt3023 regulator into a low power shutdown state. the output will be off when the pin is pulled low. the shdn1 / shdn2 pins can be driven either by 5v logic or open-col- lector logic with pull-up resistors. the pull-up resistors are required to supply the pull-up current of the open- collector gates, normally several microamperes, and the shdn1 / shdn2 pin current, typically 1a. if unused, the pin must be connected to v in . the device will not function if the shdn1 / shdn2 pins are not connected. in (pin 8): input. power is supplied to the device through the in pin. a bypass capacitor is required on this pin if the device is more than six inches away from the main input ? lter capacitor. in general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. a bypass capacitor in the range of 1f to 10f is suf? cient. the lt3023 regulator is designed to withstand reverse volt- ages on the in pin with respect to ground and the out pin. in the case of a reverse input, which can happen if a battery is plugged in backwards, the device will act as if there is a diode in series with its input. there will be no reverse current ? ow into the regulator and no reverse voltage will appear at the load. the device will protect both itself and the load. exposed pad (pin 11): ground. this pin must be soldered to the pcb and electrically connected to ground.
lt3023 9 3023fa the lt3023 is a dual 100ma low dropout regulator with micropower quiescent current and shutdown. the device is capable of supplying 100ma per channel at a dropout voltage of 300mv. output voltage noise can be lowered to 20v rms over a 10hz to 100khz bandwidth with the addition of a 0.01f reference bypass capacitor. addition- ally, the reference bypass capacitor will improve transient response of the regulator, lowering the settling time for transient load conditions. the low operating quiescent current (20a per channel) drops to less than 1a in shutdown. in addition to the low quiescent current, the lt3023 regulator incorporates several protection features which make it ideal for use in battery-powered systems. the device is protected against both reverse input and reverse output voltages. in battery backup applications where the output can be held up by a backup battery when the input is pulled to ground, the lt3023 acts like it has a diode in series with its output and prevents reverse current ? ow. additionally, in dual supply applications where the regulator load isreturned to a negative supply, the output can be pulled below ground by as much as 20v and still allow the device to start and operate. adjustable operation the lt3023 has an output voltage range of 1.22v to 20v. the output voltage is set by the ratio of two external resis- tors as shown in figure 1. the device servos the output to maintain the corresponding adj1/adj2 pin voltage at 1.22v referenced to ground. the current in r1 is then equal to 1.22v/r1 and the current in r2 is the current in r1 plus the adj1/adj2 pin bias current. the adj1/adj2 pin bias current, 30na at 25c, ? ows through r2 into the adj1/adj2 pin. the output voltage can be calculated us- ing the formula in figure 1. the value of r1 should be no greater than 250k to minimize errors in the output voltage caused by the adj1/adj2 pin bias current. note that in shutdown the output is turned off and the divider current will be zero. curves of adj1/adj2 pin voltage vs temperature and adj1/adj2 pin bias current vs temperature appear in the typical performance characteristics. the device is tested and speci? ed with the adj1/adj2 pin tied to the corresponding out1/out2 pin for an out- put voltage of 1.22v. speci? cations for output voltages greater than 1.22v will be proportional to the ratio of the desired output voltage to 1.22v: v out /1.22v. for example, load regulation for an output current change of 1ma to 100ma is C1mv typical at v out = 1.22v. at v out = 12v, load regulation is: (12v/1.22v)(C1mv) = C 9.8mv bypass capacitance and low noise performance the lt3023 regulator may be used with the addition of a bypass capacitor from v out to the corresponding byp1/ byp2 pin to lower output voltage noise. a good quality low leakage capacitor is recommended. this capacitor will bypass the reference of the regulator, providing a low frequency noise pole. the noise pole provided by this bypass capacitor will lower the output voltage noise to as low as 20v rms with the addition of a 0.01f bypass capacitor. using a bypass capacitor has the added bene? t of improving transient response. with no bypass capacitor and a 10f output capacitor, a 10ma to 100ma load step will settle to within 1% of its ? nal value in less than 100s. with the addition of a 0.01f bypass capacitor, the output will stay within 1% for a 10ma to 100ma load step (see transient reponse in typical performance characteristics section). however, regulator start-up time is proportional to the size of the bypass capacitor, slowing to 15ms with a 0.01f bypass capacitor and 10f output capacitor. figure 1. adjustable operation in 3023 f01 r2 lt3023 out1/out2 v in v out adj1/adj2 gnd r1 + vv r r ir vv ina out adj adj adj =+ + ()() = = 122 1 2 1 2 122 30 . . at 25 c output range = 1.22v to 20v applications information
lt3023 10 3023fa applications information output capacitance and transient response the lt3023 regulator is designed to be stable with a wide range of output capacitors. the esr of the out- put capacitor affects stability, most notably with small capacitors. a minimum output capacitor of 1f with an esr of 3 or less is recommended to prevent oscilla- tions. the lt3023 is a micropower device and output transient response will be a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. bypass capacitors, used to decouple individual components powered by the lt3023, will increase the effective output capacitor value. with larger capacitors used to bypass the reference (for low noise operation), larger values of output capacitors are needed. for 100pf of bypass capacitance, 2.2f of output capacitor is recommended. with a 330pf bypass capacitor or larger, a 3.3f output capacitor is recommended. the shaded region of figure 2 de? nes the region over which the lt3023 regulator is stable. the minimum esr needed is de? ned by the amount of bypass capacitance used, while the maximum esr is 3. extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are speci? ed with eia temperature char- acteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coef? cients as shown in figures 3 and 4. when used with a 5v regulator, a 16v 10f y5v capacitor can exhibit an effective value as low as 1f to 2f for the dc bias voltage applied and over the operating tempera- ture range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is avail- able in higher values. care still must be exercised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be signi? cant enough to drop capacitor values below appropriate levels. capaci- tor dc bias characteristics tend to improve as component figure 2. stability figure 4. ceramic capacitor temperature characteristics figure 3. ceramic capacitor dc bias characteristics output capacitance (f) 1 esr () 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 310 3023 f02 245 6 78 9 stable region c byp = 330pf c byp = 100pf c byp = 0 c byp > 3300pf dc bias voltage (v) change in value (%) 3023 f03 20 0 C20 C40 C60 C80 C100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f temperature (c) C50 40 20 0 C20 C40 C60 C80 C100 25 75 3023 f04 C25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f
lt3023 11 3023fa applications information case size increases, but expected capacitance at operating voltage should be veri? ed. voltage and temperature coef? cients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or micro- phone works. for a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. a ceramic capacitor produced figure 5s trace in response to light tapping from a pencil. similar vibration induced behavior can masquerade as increased output voltage noise. thermal considerations the power handling capability of the device will be limited by the maximum rated junction temperature (125c). the power dissipated by the device will be made up of two components (for each channel): 1. output current multiplied by the input/output voltage differential: (i out )(v in C v out ), and 2. gnd pin current multiplied by the input voltage: (i gnd )(v in ). the ground pin current can be found by examining the gnd pin current curves in the typical performance figure 5. noise resulting from tapping on a ceramic capacitor characteristics section. power dissipation will be equal to the sum of the two components listed above. power dissipation from both channels must be considered during thermal analysis. the lt3023 regulator has internal thermal limiting de- signed to protect the device during overload conditions. for continuous normal conditions, the maximum junction temperature rating of 125c must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction to ambient. additional heat sources mounted nearby must also be considered. for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes can also be used to spread the heat gener- ated by power devices. the following tables list thermal resistance for several different board sizes and copper areas. all measurements were taken in still air on 3/32" fr-4 board with one ounce copper. table 1. mse package, 10-lead msop copper area board area thermal resistance (junction-to-ambient) topside* backside 2500mm 2 2500mm 2 2500mm 2 40c/w 1000mm 2 2500mm 2 2500mm 2 45c/w 225mm 2 2500mm 2 2500mm 2 50c/w 100mm 2 2500mm 2 2500mm 2 62c/w *device is mounted on topside. table 2. dd package, 10-lead dfn copper area board area thermal resistance (junction-to-ambient) topside* backside 2500mm 2 2500mm 2 2500mm 2 40c/w 1000mm 2 2500mm 2 2500mm 2 45c/w 225mm 2 2500mm 2 2500mm 2 50c/w 100mm 2 2500mm 2 2500mm 2 62c/w *device is mounted on topside. the thermal resistance juncton-to-case ( jc ), measured at the exposed pad on the back of the die is 10c/w. 100ms/div v out 500v/div 3023 f05 c out = 10f c byp = 0.01f i load = 100ma
lt3023 12 3023fa applications information calculating junction temperature example: given an output voltage on the ? rst channel of 3.3v, an output voltage of 2.5v on the second channel, an input voltage range of 4v to 6v, output current ranges of 0ma to 100ma for the ? rst channel and 0ma to 50ma for the second channel, with a maximum ambient temperature of 50c, what will the maximum junction temperature be? the power dissipated by each channel of the device will be equal to: i out(max) (v in(max) C v out ) + i gnd (v in(max) ) where (for the ? rst channel): i out(max) = 100ma v in(max) = 6v i gnd at (i out = 100ma, v in = 6v) = 2ma so: p1 = 100ma(6v C 3.3v) + 2ma(6v) = 0.28w and (for the second channel): i out(max) = 50ma v in(max) = 6v i gnd at (i out = 50ma, v in = 6v) = 1ma so: p2 = 50ma(6v C 2.5v) + 1ma(6v) = 0.18w the thermal resistance will be in the range of 40c/w to 60c/w depending on the copper area. so the junction temperature rise above ambient will be approximately equal to: (0.28w + 018w)(60c/w) = 27.8c the maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: t jmax = 50c + 27.8c = 77.8c protection features the lt3023 regulator incorporates several protection features which makes it ideal for use in battery-powered circuits. in addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the devices are protected against reverse input voltages, reverse output voltages and reverse voltages from output to input. current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. for normal operation, the junction temperature should not exceed 125c. the input of the device will withstand reverse voltages of 20v. current ? ow into the device will be limited to less than 1ma (typically less than 100a) and no negative voltage will appear at the output. the device will protect both itself and the load. this provides protection against batteries which can be plugged in backward. the output of the lt3023 can be pulled below ground without damaging the device. if the input is left open circuit or grounded, the output can be pulled below ground by 20v. the output will act like an open circuit; no current will ? ow out of the pin. if the input is powered by a voltage source, the output will source the short-circuit current of the device and will protect itself by thermal limiting. in this case, grounding the shdn1 / shdn2 pins will turn off the device and stop the output from sourcing the short- circuit current. the adj1 and adj2 pins can be pulled above or below ground by as much as 7v without damaging the device. if the input is left open circuit or grounded, the adj1 and adj2 pins will act like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground. in situations where the adj1 and adj2 pins are connected to a resistor divider that would pull the pins above their 7v clamp voltage if the output is pulled high, the adj1/adj2 pin input current must be limited to less than 5ma. for example, a resistor divider is used to provide a regulated 1.5v output from the 1.22v reference when the output is forced to 20v. the top resistor of the resistor divider must be chosen to limit the current into the adj pin to less than 5ma when the adj1/adj2 pin is at 7v. the 13v difference between output and adj1/adj2 pin divided by the 5ma maximum current into the adj1/adj2 pin yields a minimum top resistor value of 2.6k.
lt3023 13 3023fa c byp (pf) 10 0.1 startup time (ms) 1 10 100 100 1000 10000 3023 ta02c v shdn1 / shdn2 1v/div v out1 1v/div v out2 1v/div 2ms/div 3023 ta02b out1 byp1 adj1 out2 byp2 adj2 in shdn1 shdn2 lt3023 1f v in 3.7v to 20v off on 0.01f 0.01f 422k 261k 249k 249k 10f 10f 3023 ta02a 3.3v at 100ma 2.5v at 100ma gnd typical applications applications information in circuits where a backup battery is required, several different input/output conditions can occur. the output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. current ? ow back into the output will follow the curve shown in figure 6. when the in pin of the lt3023 is forced below the out1 or out2 pins or the out1/out2 pins are pulled above the in pin, input current will typically drop to less than 2a. this can happen if the input of the device is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. the state of the shdn1 / shdn2 pins will have no effect on the reverse output current when the output is pulled above the input. figure 6. reverse output current noise bypassing slows startup, allows outputs to track startup time output voltage (v) 100 90 80 760 60 50 40 30 20 10 0 reverse output current (a) 3023 f06 0123 4 5 67 8910 t a = 25c v in = 0v v out = v adj current flows into output pin
lt3023 14 3023fa package description 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699)
lt3023 15 3023fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description mse package 10-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1664 rev b) msop (mse) 0307 rev b 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ?.011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) 0.1016 0.0508 (.004 .002)
lt3023 16 3023fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2003 lt 0208 rev a ? printed in usa v shdn1 1v/div v out1 1v/div v out2 1v/div 2ms/div 3023 ta03c out1 byp1 adj1 out2 byp2 adj2 in shdn1 shdn2 lt3023 1f v in 3.7v to 20v off on 0.01f 0.01f 422k 261k 249k 249k 35.7k 28k 10f 10f 3023 ta03a 3.3v at 100ma 2.5v at 100ma gnd 0.47f related parts typical application v shdn1 1v/div v out1 1v/div v out2 1v/div 2ms/div 3023 ta03b startup sequencing turn-on waveforms turn-off waveforms part number description comments lt1129 700ma, micropower, ldo v in : 4.2v to 30v, v out(min) = 3.75v, i q = 50a, i sd = 16a, dd, sot-223, s8,to220, tssop20 packages lt1175 500ma, micropower negative ldo guaranteed voltage tolerance and line/load regulation, v in : C20v to C4.3v, v out(min) = C3.8v, i q = 45a, i sd = 10a, dd,sot-223, s8 packages lt1185 3a, negative ldo accurate programmable current limit, remote sense, v in : C35v to C4.2v, v out(min) = C2.40v, i q = 2.5ma, i sd <1a, to220-5 package lt1761 100ma, low noise micropower, ldo low noise < 20v rms, stable with 1f ceramic capacitors, v in : 1.8v to 20v, v out(min) = 1.22v, i q = 20a, i sd <1a, thinsot package lt1762 150ma, low noise micropower, ldo low noise < 20v rms, v in : 1.8v to 20v, v out(min) = 1.22v, i q = 25a, i sd <1a, ms8 package lt1763 500ma, low noise micropower, ldo low noise < 20v rms, v in : 1.8v to 20v, v out(min) = 1.22v, i q = 30a, i sd <1a, s8 package lt1764/lt1764a 3a, low noise, fast transient response, ldo low noise < 40v rms, "a" version stable with ceramic capacitors, v in : 2.7v to 20v, v out(min) = 1.21v, i q = 1ma, i sd <1a, dd, to220 packages ltc1844 150ma, very low drop-out ldo low noise < 30v rms , stable with 1f ceramic capacitors, v in : 1.6v to 6.5v, v out(min) = 1.25v, i q = 40a, i sd <1a, thinsot package lt1962 300ma, low noise micropower, ldo low noise < 20v rms, v in : 1.8v to 20v, v out(min) = 1.22v, i q = 30a, i sd <1a, ms8 package lt1963/lt1963a 1.5a, low noise, fast transient response, ldo low noise < 40v rms, "a" version stable with ceramic capacitors, v in : 2.1v to 20v, v out(min) = 1.21v, i q = 1ma, i sd <1a, dd, to220, sot-223, s8 packages lt1964 200ma, low noise micropower, negative ldo low noise < 30v rms, stable with ceramic capacitors, v in : C0.9v to C20v, v out(min) = C1.21v, i q = 30a, i sd = 3a, thinsot package ltc3407 dual 600ma. 1.5mhz synchronous step down dc/dc converter v in : 2.5v to 5.5v, v out(min) = 0.6 v, i q = 40a, i sd <1a, mse package

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